KWALIFIKACJA ELM2 - TEST WIEDZY NR 9

entity AND_GATE is
port(
    A : in STD_LOGIC;
    B : in STD_LOGIC;
    Z : out STD_LOGIC
);
end AND_GATE;

architecture AND_GATE_ARCH of AND_GATE is
begin
    Z <= A and B;
end AND_GATE_ARCH;